基于28nm CMOS工艺的鉴频鉴相器和电荷泵设计  

The Design of Phase Frequency Detector and Charge Pump Based on 28 nm CMOS Process

作　　者：谢灿[1,2] 黄水龙[1,2] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]新一代通信射频芯片技术北京市重点实验室,北京100029

出　　处：《微电子学与计算机》2016年第12期57-61,共5页Microelectronics & Computer

基　　金：国家科技重大专项02专项(2014ZX02302002)

摘　　要：基于SMIC 28nm CMOS工艺,完成了高性能鉴频鉴相器和电荷泵的设计.采用D触发器型鉴频鉴相器结构,通过优化其门电路结构,获得了一种两路输出信号具有良好匹配性能的鉴频鉴相器.采用源极开关的电荷泵结构,同时在该结构中采用轨到轨输入级的运放,获得了一种在较大的输出电压范围内都具有低失配电流的电荷泵.The design of high-performance Phase Frequency Detector and Charge Pump based on SMIC 28 nm CMOS process has been achieved in this paper. By using D flip-flop PFD and optimizing structure of the gate, a PFD has been accomplished, which two output had a good matching performance. To obtain a CP with low mismatch current under the larger range of output voltage, source-switch CP structure and an operational amplifier with a rail-to-rail input stage were used.

关 键 词：高性能 鉴频鉴相器 电荷泵 源极开关 电流失配 

分 类 号：TN4[电子电信—微电子学与固体电子学]