基于分布式算法的多项抽取滤波器设计  

Design of polyphase decimation filter based on distributed algorithm

作　　者：石立国[1,2] 侯鸿杰 王竹刚[1] 熊蔚明[1] 

机构地区：[1]中国科学院国家空间科学中心,北京100190 [2]中国科学院大学,北京100190

出　　处：《现代电子技术》2016年第23期68-71,共4页Modern Electronics Technique

基　　金：国家高技术研究发展计划(863计划)(Y28021A220)

摘　　要：实现高阶FIR滤波器时,在降低FPGA硬件资源占用方面,分布式算法和多相分解技术应用广泛。详细介绍了分布式算法和多相分解技术的原理,并结合FPGA的特点提出了适用于高阶FIR滤波器的新算法,解决了分布式算法实现高阶FIR滤波器查找表过大的问题,提高了硬件资源的利用率。推导了基于分布式算法和多相分解技术的实现原理,通过ISE实现并验证了该算法的高效性。最后,给出了滤波器性能随滤波器系数量化位宽变化的关系。The distributed algorithm and polyphase decomposition technology are widely used to implement the high-order FIR filter and reduce the occupancy of FPGA hardware resource. The principles of the distributed algorithm and polyphase de- composition technology are introduced in detail. In combination with the characteristics of FPGA, a new algorithm suitable for high-order FIR filter is proposed, which can solve the problem that the distributed algorithm is adopted to realize the oversize high-order FIR filter lookup table, and improve the utilization of hardware resource. The implementation principles based on the distributed algorithm and polyphase decomposition technology are deduced. The high efficiency of this algorithm was realized and verified by ISE. The relationship of variation of the filter performance with the width of the filter coefficient quantization bit is given.

关 键 词：FIR滤波器 FPGA 分布式算法 多相分解 

分 类 号：TN713.734[电子电信—电路与系统]