锁频环加锁相环方案的设计和实现  

Design and Implement of PLL with FLL

作　　者：胡骥[1] 程明[1] 叶宝盛[1] 杨德远[1] 

机构地区：[1]中国电子科技集团公司第三十六研究所,浙江嘉兴314033

出　　处：《通信对抗》2016年第2期30-33,共4页Communication Countermeasures

摘　　要：对锁频环的工作原理进行研究,建立了锁频环的数学模型,并对锁相环+锁频环方案的相位噪声性能进行了分析,在小数分频锁相环中加入了锁频环电路,最终实现了对环路相位噪声的优化。In this paper ,the Frequency Lock Loop （FLL）was investigated and the mathematics model of the FLL was analyzed . Also the phase noise of the PLL with FLL was analyzed. In the actual circuit,a FLL circuit was involved in a Fractional-N pll circuit.And finally the phase noise was optimized successfully.

关 键 词：锁频环 延迟线鉴相器 超低相噪 

分 类 号：TN74[电子电信—电路与系统]