高速低功耗CORDIC算法的研究与实现  

Research and implementation of the high-speed and low-power dissipation CORDIC algorithm

作　　者：胡普华[1,2] 赵建龙[1,2] 罗炬锋[1] 李强 

机构地区：[1]中国科学院上海微系统与信息技术研究所传感技术联合国家重点实验室,上海200050 [2]上海科技大学,上海200120 [3]上海物联网中心,上海201800

出　　处：《电子设计工程》2016年第24期144-147,共4页Electronic Design Engineering

基　　金：上海市浦江人才计划资助(14PJ1433100)

摘　　要：针对传统CORDIC算法流水线结构的迭代次数过多,运算速度不够快,消耗硬件资源较多的缺点,改进了一种基于旋转模式并行运算的CORDIC算法。该算法采用二进制两极编码和微旋转角编码进行低位符号预测和高符号位预测,并且在高符号位预测过程中,对误差进行了校正。在FPGA实现中,采取三段式实现方法,与传统方法相比,有效地减少计算的级数和降低硬件资源的功耗,达到了高速低功耗的要求。In this paper, a new parallel coordinate rotation digital computer （CORDIC） rotation algorithm in circular is proposed. The rotation number of conventional CORDIC algorithm is too large and the conventional algorithm is not efficiency. In order to improve the CORDIC algorithm, we use the binary-to-bipolar recoding （BBR） and microrotation angle recoding （MAR） to predict the lower part and higher part of the direction of rotation. Compared to conventional CORDIC algorithm, the proposed method needs fewer iterations and less hardware resources and operates faster. The lower sign precomputation and higher sign precomputation is processed respectively and error correction is done during the high sign bit prediction. The three-phase implementation method is applied on FPGA, which can reduce the operation series and power consumption effectively and meets the requirement of high-speed and low-power dissipation.

关 键 词：FPGA 符号预测 低功耗 二进制两极编码 微旋转角编码 

分 类 号：TN911.7[电子电信—通信与信息系统]