一种嵌入式处理器间SPI总线通信优化方法  

A SPI Bus Communication Optimization Method between Embedded Processors

作　　者：白林亭 海钰琳[1] 李亚晖[1,2] BAI Lin- ting HAl Yu- lin LI Ya- hui(Xi＇an Aeronautics Computing Technique Research Institute, A VIC, Xi＇an 710068, China Aviation Key Laboratory of Science and Technology on Airborne and Missleborne Computer, Xi＇an 710068, China)

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710068 [2]机载弹载计算机航空科技重点实验室,陕西西安710068

出　　处：《航空计算技术》2016年第6期103-107,共5页Aeronautical Computing Technique

基　　金：中航工业技术创新基金项目资助(2014D63130R);航空科学基金项目资助(2015ZC31005)

摘　　要：SPI(Serial Peripheral Interface,串行外设接口)作为一种全双工的同步通信总线,常用于嵌入式处理器间的通信。提出一种在P2020处理器与基于Xilinx K7 FPGA芯片的软核处理器间的SPI总线通信优化方法。利用SPI总线双向同步传输的特点,提出一种简易且有效的通信协议保证通信质量;根据SPI总线两端处理器的时钟频率,设置SPI总线波特率,提升数据传输速率;同时,考虑SPI总线两端处理器的处理频率的差异,设置合理数据传输延迟,保证数据传输的正确性和稳定性。实验结果表示,该SPI总线通信方法在上述平台中能够达到750KR/S的通信速率,能够满足多种嵌入式平台的数据传输需求。As a full- duplex synchronous communication bus, SPI is widely used in embedded inter- pro- cessor communication. In this paper, a new SPI communication method between the P2020 processor and soft- core processor on Xilinx K7 FPGA is proposed. Based on the feature of SPI bus, a simple but efficient communication principle is proposed to guarantee the communication quality, and the baud rate of SPI is fineset based on the clock rate of processors to improve the transfer speed. In addition, the transfer delay between each unit must be reasonable to guarantee the data correctness and stabilization, as the clock rate of P2020 and is different. The experimental results have shown that, the communication speed of the method in this paper can reach up to750KB/s, which can satisfy the data transfer demand of em- bedded inter- processor communication.

关 键 词：SPI总线 通信协议 波特率 传输延迟 

分 类 号：TN915.04[电子电信—通信与信息系统]