基于FPGA的CCSDS位平面编码设计与实现  

Design and Implementation of Bit-plane Encoding for CCSDS Based on FPGA

作　　者：王娟[1,2] 胡永刚[2] 吴宪祥[2] 

机构地区：[1]西安翻译学院工程技术学院,西安710105 [2]西安电子科技大学空间科学与技术学院ICIE研究所,西安710071

出　　处：《微型电脑应用》2016年第12期4-7,共4页Microcomputer Applications

基　　金：国家自然科学基金项目(61105066);中央高校基本科研业务费专项资金资助项目(JB141305)

摘　　要：针对已有位平面编码实现存在扫描效率低、复杂度高等缺点,提出了一种基于CCSDS图像压缩算法位平面编码技术的FPGA实现方法。将CCSDS图像压缩算法位平面编码分为预处理、扫描、熵编码等几个关键模块,采用流水结构对系统进行设计。最后,用Modelsim进行仿真测试,经检验,输出的编码结果正确。实验表明,提出的实现方案编码效率高,复杂度低,有一定的实用价值。Aiming at overcoming the shortcomings of low scan efficiency and high complexity that exist in bit-plane coding, a bit-plane coding module in CCSDS image compression is proposed and implemented based on FPGA. Bit-plane coding in CCSDS image compression is composed of several key modules including pretreatment, scan, entropy coding, etc. Besides, the architecture in pipeline is adopted to design the system. Finally, the simulation is carried out by Modelsim, and the encoding result is turned out to be correct. The experimental results show that the implementation scheme proposed in this paper has high encoding efficiency, low complexity, thus it has great practical value.

关 键 词：CCSDS 图像压缩 位平面编码 FPGA 

分 类 号：TP751.1[自动化与计算机技术—检测技术与自动化装置]