一种用于10Gb/s Serdes的40nm CMOS锁相环  

A PLL for 10Gb/s Serdes in 40nm CMOS Process

作　　者：刘认 罗林[1] 孟煦[1] 刁盛锡[1] 林福江[1] LIU Ren LUO Lin MENG Xu DIAO Shengxi LIN Fujiang(Department of Electronic Science and Technology, Univ. of Sci. and Technol. of China, Hefei 230027, P. R. Chin)

机构地区：[1]中国科学技术大学电子科学与技术系,合肥230027

出　　处：《微电子学》2016年第6期767-771,共5页Microelectronics

基　　金：联发科对该项目的支持

摘　　要：提出了一种应用于10Gb/s高速串并接口电路(Serdes)的高性能锁相环。采用正交压控振荡器(QVCO)实现4路等相位间隔的5GHz时钟,输出采用2分频单转差缓冲器,实现可忽略相差的8路等相位间隔的2.5GHz时钟。电荷泵中采用负反馈技术,以提高电流匹配性能。在SMIC 40nm工艺下完成设计,在1.1V的供电电压下,锁相环的总电流为7.6mA,输出5GHz时钟在10kHz^100 MHz积分范围内的均方根抖动约为107fs,芯片尺寸仅为780μm×410μm。A low jitter phase-locked loop（PLL）for 10Gb/s serial/deserial（Serdes）application was presented.Quadrature voltage-controlled oscillator（QVCO）had been employed to generate 4-phases 5GHz clocks in the PLL.Then the/2divider and single-to-differential buffers were used to generate 8-phases 2.5GHz clocks with negligible phase error.Negative feedback technique had been used in the charge pump to improve up/down current mismatch.The PLL was implemented in SMIC 40 nm CMOS process.It consumed 7.6mA current from a 1.1Vsupply.The RMS output jitter of 5GHz output clock that was integrated from 10 kHz to 100 MHz was 107 fs.The die area was only 780μm×410μm.

关 键 词：CMOS锁相环 低抖动 多相时钟 正交LC压控振荡器 

分 类 号：TN432[电子电信—微电子学与固体电子学]