一种自适应带宽低抖动PLL设计  

Design of a Low Jitter Adaptive Bandwidth PLL

作　　者：陈啟宏 杨淼[1] 秦昌兵[1] 张白雪[1] 任建雄[1] 洪乙又[1] CHEN Qihong YANG Miao QIN Changbing ZHANG Baixue REN Jianxiong HONG Yiyou(Nanjing Electronic Devices Institute, Nanjing 210016, P. R. China)

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《微电子学》2016年第6期772-776,共5页Microelectronics

摘　　要：设计了一种宽调节范围自适应带宽的低抖动锁相环倍频器（PLL）。通过采用自偏置技术,使得电荷泵电流和运算放大器的输出阻抗随工作频率成比例变化,从而使阻尼因子保持固定、环路带宽跟随输入参考频率自动调整,以及PLL在整个输出频率范围内保持最佳的抖动性能。电路采用SMIC 0.18μm CMOS工艺进行设计,后仿真验证表明,该PLL电路能够在0.35~2.1GHz的输出频率范围内输出良好的低抖动信号,输出频率为2.1GHz时,均方根抖动为2.47ps。A low-jitter adaptive bandwidth PLL with wide tuning range was presented.The current of charge pump and the output resistance of regulating amplifier were made to be proportional to the operating frequency with self-biased techniques,so that the damping factor was fixed and the loop bandwidth was scaled with the reference frequency.The proposed PLL maintained optimal jitter performance over whole operating range.The circuit was designed in the SMIC 0.18 μm CMOS process.Post simulation results showed that the PLL had good jitter performance within operating frequency range from 350 MHz to 2.1 GHz.When the output frequency was 2.1GHz,the RMS jitter was 2.47 ps.

关 键 词：锁相环 自适应带宽 自偏置 低抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学]