基于PCI Express总线的同步时钟卡的设计与实现  

Design and implementation of synchronous clock card based on PCI Express bus

作　　者：陈永志[1] 魏丰[1] 王旭东[1] 

机构地区：[1]华中科技大学自动化学院,湖北武汉430074

出　　处：《电子设计工程》2017年第1期106-109,共4页Electronic Design Engineering

摘　　要：本文介绍了一种基于PCI Express(简称PCI-E)总线的同步时钟卡的设计与实现,简要叙述了自行研发的PCI-E同步时钟卡的系统架构及工作原理。基于本卡小批量数据传输和响应中断的特点,提出一种用CH367芯片联合单片机、双口RAM、CPLD等芯片来设计GPS同步时钟卡的硬件设计方案,并用VC++开发设计应用软件用于满足时间的测试与显示需求。测试结果证明同步时钟卡工作稳定,保证了数据传输的连续性和完整性。The paper introduces a design and implementation of synchronous clock card based on PCI Express（Abbreviated for PCI-E） bus, and describes briefly the system architecture and works on our own PCI-E synchronous clock card. Based on the characteristics of small batch data transmission and interrupt response of this card, the design uses the CH367 chip, microcontroller, dual port RAM, CPLD and other chips to complete the hardware circuit of the GPS synchronous clock card, then designs application interface to satisfy time test and display by VC＋＋.Finally,test results proved that the synch- ronous clock card works stably ,which ensure continuous data receiving and the integrality of the data.

关 键 词：PCI EXPRESS总线 CH367 小批量数据 同步时钟卡 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]