高稳可变频率源的低杂散设计与实现  

Low spurious design and implement of a high-stability and adjustable frequency source

作　　者：解东亮[1] 潘明海[1] 王龙[1] 

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京210016

出　　处：《航天电子对抗》2016年第6期49-53,共5页Aerospace Electronic Warfare

基　　金：国家自然科学基金(61271327);江苏高校优势学科建设工程项目资助课题

摘　　要：现代雷达电子对抗广泛使用DRFM对雷达信号进行采样、存储与处理。传统频率合成技术无法同时满足高性能DRFM对频率信号的稳定、低杂散、多路相参等指标要求。研究了频率源输出信号的抖动与杂散谐波对采样系统杂散性能的影响，结合传统频率合成技术，设计了基于FPGA和低噪声时钟抖动消除器的频率源电路，并对初级信号的谐波抑制设计了基于带通滤波器和微带滤波器的窄带滤波电路。最后，对系统的测试结果表明，本设计可输出多路频率范围为2．27～2600MHz（分段）的频率信号，步进小于10kHz。信号相位噪声优于—95dBc／Hz@100kHz，杂散抑制优于—60dBc。DRFM is widely used to sample, store and process radar signals in modern radar electronic coun- termeasure. The traditional frequency synthesis cannot satisfy the requirements of the high-performance DRFM simultaneously to the stability, low spurious and multi-channel synchronization of frequency signal. The effect of the jitter and harmonic component of frequency signal to the sample system spurious performance is studied, and the frequency source based on FPGA and low noise compliant clock jitter cleaner is proposed by combining the traditional frequency synthesis. Furthermore, the narrow band filter based on band-pass filter and microstrip filter are designed to suppress the harmonic component of original signal. According to the measurement results, multi-channel frequency signal within 2.27～2600MHz is generated. The step frequency is less than 10kHz, and phase noise is better than -95dBc/Hz@100kHz, and harmonic suppression is better than -60dBc.

关 键 词：频率源 低杂散 谐波抑制 滤波电路 

分 类 号：TN74[电子电信—电路与系统]