乱序超标量处理器核的功耗优化  

Power optimization of an out-of-order superscalar processor core

作　　者：孙彩霞[1] 李文哲[1] 高军[1] 王永文[1] SUN Cai-xia LI Wen-zhe GAO Jun WANG Yong-wen(College of Computer, National University of Defense Technology,Changsha 410073 ,China)

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2017年第1期49-54,共6页Computer Engineering & Science

基　　金：国家自然科学基金(61103011)

摘　　要：为了追求更高的性能,处理器核的主频不断提升,处理器核的设计日益复杂,随之而来的是功耗问题越来越突出。除了在工艺级和电路级采用低功耗技术外,在逻辑设计阶段通过分析处理器核各个功能模块的特点并采用相应的技术手段,也可以有效降低功耗。对一款乱序超标量处理器核中功耗比较突出的模块——寄存器文件和再定序缓冲——进行了逻辑设计优化,在程序运行性能几乎不受影响的情况下明显减少了面积,降低了功耗。To maximize the performance, the frequency of the processor core becomes increasingly higher, and the design of the processor core gets much more complex. As a result, power issues become a challenge and need special care. Beside process-level and circuit-level low power technologies, adopting some strategies according to the features of modules during the RTL design can reduce power consumption. We analyze the power of an out-of-order superscalar processor core and optimize the designs of register files and the reorder buffer based on the analysis. Evaluation results show that the area and power of the processor core decrease with no obvious performance penalty.

关 键 词：乱序 超标量 性能 功耗 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]