一种基于矩阵的并行CRC校验算法  

Parallel CRC verification algorithm based on matrix

作　　者：赵坤鹏[1] 吴龙胜[1] 马徐瀚 陈庆宇[1] ZHAO Kun-peng WU Long-sheng MA Xu-han CHEN Qing-yu(Xi＇an Microelectronics Technology Institute, Xi＇an 710054, China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《电子设计工程》2017年第3期85-88,共4页Electronic Design Engineering

摘　　要：针对高速网络通信中高位宽并行数据的实时校验需求,提出了一种可单周期实现的、面向128位并行数据的循环冗余校验算法(Cyclic Redundancy Check,CRC)。该算法首先根据CRC串行编码原理得到8位并行数据的CRC校验矩阵,之后对矩阵进行迭代简化,得到32位并行数据的参数矩阵,此参数矩阵作为该CRC算法的核心实现了对数据进行预处理。最后对该算法进行了硬件实现,仿真及综合结果表明,该算法可在单周期内完成对128位并行数据的CRC编码和解码校验,时钟频率提高1.8倍,而硬件开销仅增加5.15%。To target the real-time verification requirement of the parallel data in the high speed network communication, the CRC （Cyclic Redundancy Check） algorithm which can implement cheek of 128-bit parallel data in a single cycle is presented in this paper. Firstly, the CRC check matrix for 8-bit parallel data is extrapolated base on the principle of CRC serial encoding. Then, that check matrix is iteratively simplified to calculate the parameter matrix of 32-bit parallel data. The parameter matrix is regarded as the most significant part in the proposed algorithm and is used to pre-process data. Finally, the algorithm is implemented by hardware. The results of simulation and synthesis show that the encoding and decoding check of 128-bit parallel data can be finished in a single cycle based on the proposed algorithm and the clock frequency increases by 1.8 times with the hardware overheads only.increasing 5.15%.

关 键 词：128位并行数据 单周期 CRC算法 硬件实现 频率提高 

分 类 号：TN492[电子电信—微电子学与固体电子学]