向导滤波器的整数FPGA设计结构  

An integer FPGA architecture of guided filtering

作　　者：刘祝华[1] 袁文[1] 

机构地区：[1]江西师范大学物理与通信电子学院,江西南昌330022

出　　处：《计算机工程与科学》2017年第2期336-342,共7页Computer Engineering & Science

基　　金：国家自然科学基金(11264016)

摘　　要：对一种单图像向导滤波器的高性能FPGA设计结构进行了分析,发现其中的均值滤波器存在设计缺陷,据此提出了一种向导滤波器的整数FPGA设计结构。通过改变均值滤波器的数据累加顺序,减少了存储资源的使用,同时以整数数据处理方式实现了向导滤波器中方差和变换系数的计算,并且通过参数调整,可以方便地实现不同大小图像的不同尺寸窗口的向导滤波。在Altera公司Cyclone系列FPGA芯片上进行了综合,实验结果表明,向导滤波整数FPGA结构的处理结果与浮点计算四舍五入取整后的结果相比,最大误差不超过1,同时新结构大幅度降低了硬件资源的使用量,有效提升了数据处理速度,使用EP3C40F484C8芯片综合时,能以高达162fps的速度处理1024×1024的图像,能很好地满足各种图像实时处理要求。We analyze a high performance FPGA architecture of guided filtering for single image and find out that the mean filter of guided filtering has design defects. For this reason, we propose an inte- ger FPGA architecture of guided filtering. Changing the sequence of data accumulation of the mean filter can reduce the use of memory on the FPGA. At the same time, we calculate the variance and transform coefficients of guided filtering by integer processing. Moreover, the size of image and filtering window can be changed flexibly via parameter adjustment. We implement the new architecture on the FPGA of Altera＇s Cyclone, and experimental results show that the maximum error between the integer FPGA architecture＇ processing result and the floating-point calculation result after rounding off is less than one. The new architecture greatly reduces the use of hardware resource and effectively improves the speed of data processing. When be implemented on the EP3C40F484C8, it is capable of processing images with dimension of 1024 by 1024 at the frame rate of 162 FPS, and can well meet the requirements of all kinds of real-time image processing.

关 键 词：向导滤波 FPGA 整数处理 均值滤波 图像处理 

分 类 号：TN713.7[电子电信—电路与系统]