一种高速低功耗双电流锁存比较器  

A High Speed Low Power Double Tail Latch Comparator

作　　者：唐小丽 段吉海 徐卫林 向指航 

机构地区：[1]广西精密导航技术与应用重点实验室,广西桂林541004

出　　处：《微电子学》2017年第1期50-54,共5页Microelectronics

基　　金：广西自然科学基金资助项目(2013GXNSFAA019333;2014GXNSFAA019333);国家自然科学基金资助项目(61161003;61264001;61166004)

摘　　要：提出了一种应用于低电源电压的改进型高速超低功耗双电流动态锁存比较器。在不增加电路复杂度的情况下,通过在传统双电流动态比较器中增加一条额外的放电途径,使得比较器能够快速地从复位状态进入到再生阶段,缩短了整个过程的延迟时间,更重要的是扩宽了输入共模范围,同时降低了延迟时间对共模输入电压的依赖性。电路基于SMIC 0.18μm CMOS工艺进行设计与仿真,仿真结果表明,在时钟频率为1GHz,输入电压差为5mV时,延迟时间为294ps,功耗仅为52μW。An improved high speed ultra low power double tail dynamic latch comparator was proposed for the applications of low supply voltages. The circuit＇s complexity was not increased, and an extra discharge pathway was added only in the traditional dual current dynamic comparator. So the regeneration phase of comparator was accelerated from the reset state, which had resulted in reduced delay times of the whole process. It＇s more important that the input common mode range was widened, and the dependence of delay time on the common mode input voltage was reduced. The proposed circuit was designed and simulated in SMIC 0.18μm CMOS process. Simulation results showed that the delay time of the dynamic comparator was 294 ps. It consumed only 52 μW when the clock frequency was 1 GHz and the input voltage difference was 5 inV.

关 键 词：双电流 锁存比较器 高速 低功耗 延迟时间 

分 类 号：TN432[电子电信—微电子学与固体电子学]