采用快速建立双电荷泵技术的扩频时钟产生器设计  

Design of a Low Jitter Fraction-N SSCG Based on Fast-setting Dual Charge Pump Technology

作　　者：龙强[1,2] 田泽[1,2] 王晋[1,2] 唐龙飞[1,2] LONG Qiang TIAN Ze WANG Jin TANG Long-fei(Aeronautical Computing Technique Research Institute of AVIC, Xi＇an Shaanxi 710068, China Aeronautical Science and Technique Key laboratory of Integrate Circuit and Micro-system Design, Xi＇an Shaanxi 710068, China)

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710068 [2]集成电路与微系统设计航空科技重点实验室,陕西西安710068

出　　处：《无线电工程》2017年第3期66-69,共4页Radio Engineering

基　　金：总装备部预研基金资助项目(9140A08010712HK6101)

摘　　要：传统的扩频时钟产生器具有较长的建立时间,同时芯片面积较大。针对上述问题,给出了一种采用快速建立双电荷泵技术的低抖动分数扩频时钟产生器(SSCG)的设计。快速建立双电荷泵技术不但可以减小芯片面积,而且通过控制SSCG建立过程中电荷泵(CP)的工作顺序来缩短建立时间。SSCG中的多模分频器采用差分动态触发器技术来减小芯片面积,降低功耗和抖动。SSCG采用0.13μm CMOS工艺制造,3.91μs的建立时间远快于采用传统SSCG技术的8.11μs,在1.5 GHz 250个周期内随机抖动和总抖动分别为2.7 psrms和3.3 psrms。EMI减小了10 d B,符合SATA的技术要求。芯片面积为0.3 mm×0.7 mm,功耗为18 m W。测试结果表明,采用快速建立双电荷泵技术,建立时间大幅度缩短,芯片面积也有了较大的优化。The traditional spread spectrum clock generating appliances need a long build time and large chip area.To solve this problem,a low jitter fraction-N spread spectrum clock generator （SSCG） which adopts the technology of fast-setting dual charge pump （CP） is presented in this paper.This technology not only reduces a design area but also shortens setting time by controlling the CP operation sequence in an SSCG setting period. A modulus divider using differential dynamic flip-flop in SSCG can reduce the area occupation,power dissipation and jitter.SSCG is fabricated with 0.13 μm CMOS process.The setting time was 3.91 μs,which faster than the conventional SSCG of 8.11μs.The random jitter and total jitter in 250 cycles at 1.5 GHz is 2.7 psrms and 3.3 psrms,respectively. The EMI decreases 10 dB, meeting the technical requirement of SATA. The area and power dissipation is 0.3 mm ＊ 0.7 mm and 18 mW,respectively.Test results demonstrate that this fast-setting dual charge pump technology could shorten setting time and reduce chip area.

关 键 词：扩频时钟产生器 电荷泵 抖动 SATA 电磁兼容 

分 类 号：TN792[电子电信—电路与系统]