ZDPS-2实时高可靠综合电子系统的逻辑架构设计  

Logical architecture design of integrated electronic system with high real-time and reliability in ZDPS-2 pico-satellite

作　　者：苏星[1] 王慧泉[1] 金仲和[1] 

机构地区：[1]浙江大学微小卫星研究中心,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2017年第3期628-636,共9页Journal of Zhejiang University：Engineering Science

摘　　要：针对ZDPS-2卫星的高实时性要求,设计多路并行独占式DMA,实现CPU与包括载荷在内的所有部件的高效交互:54路外设串行接口通信占用CPU时间由565ms降低到50ms,姿控系统传感器数据采集时间一致性由33ms降低到6ms.设计数据混编传输机制及链式DMA结构,实现84路载荷数据100 Hz高频采集与实时下传,满足40ms下传延时要求.通过关键器件抗辐射加固及系统容错机制,提高系统的可靠性.地面测试与在轨运行结果表明:综合电子系统功能正确,稳定可靠,已在轨连续运行5个多月,完成了载荷及各项试验,实时性满足任务需求.As high-real-time and reliability was required in ZDPS-2,multiple exclusive DMA modules were designed to work in parallel way for effective communication between CPU and all the peripherals by 54 serial interfaces.Experiments show that the time consumption on 54 interfaces between CPU and peripherals is reduced from 565 ms to 50 ms,and the sampling time difference among all sensors of ADCS is reduced from 33 ms to 6ms.Special frame structure and linked-list-based DMA modules can meet the real-time requirement of 84distributed-payloads,the data sampling rate on 84distributed-payloads reaches100 Hz,and the transmitting latency to the ground is less than 40 ms.Radiation-hardened and faulttolerant designs were also applied to improve the reliability.The ground test and on-orbit operation show that the integrated electronic system functions correctly and the system is stable and reliable.The system has been running continuously for more than five months to complete all payload tests.The real-time performance meets the mission requirement well.

关 键 词：ZDPS-2 实时性 可靠性 皮纳卫星 综合电子系统 FPGA 

分 类 号：V423.43[航空宇航科学与技术—飞行器设计]