数字锁相放大器优化设计与仿真研究  

The Optimization Design and Simulation Study of Digital Lock-in Amplifier

作　　者：朱卫华[1] 陈权[1] 刘国稳 

机构地区：[1]南华大学电气工程学院,湖南衡阳421001

出　　处：《仪表技术》2017年第2期18-21,共4页Instrumentation Technology

基　　金：湖南省自然科学基金资助项目(2015JJ6098)

摘　　要：为了减少数字锁相放大器中的数字信号处理模块在硬件实现时所占用的逻辑资源,采用多抽样率数字信号处理理论来降低被测信号的采样频率,设计了高性能的数字窄带低通滤波器。利用Hogenaur"剪除"理论的级联积分梳状(Cascade Integrator Comb,CIC)滤波器,在FPGA实现时不仅能够节省大量的硬件逻辑资源,而且提高了CIC滤波器的最小响应时间;利用内插二阶多项式滤波器(Interpolated Second Order Pofynomials,ISOP)使CIC滤波器通带衰减降低到0.4 dB左右。MATLAB与Modelsim联合仿真测试验证了设计的正确性与可行性。In order to reduce hardware logic resources occupied by the digital signal processing module of digital lock-in amplifier, multi-rate signal processing technology is used to reduce the sampling frequency of measured signal and then one digital narrowband low pass filter is designed with high performance. The implementation of the cascade integral comb filter using the theory of Hogenaur ＂cut off＂, not only can save a lot of hardware logic resources, but also can increase the minimum response time. The interpolated second-order polynomials filter is adopted to compensate the pass band attenuation of CIC filter and to reduce the passband to about 0.4 dB. Matlab and Modelsim co-simulation testing verifies the correctness and feasibility of the design.

关 键 词：数字锁相放大器 级联积分梳状滤波器 内插二阶多项式滤波器 “剪除”理论 

分 类 号：TN713[电子电信—电路与系统]