一种低功耗相位切换型分频器  

Low power phase-switching prescaler

作　　者：吉新村[1] 夏晓娟[1] 徐严[1] 胡伟[1] 

机构地区：[1]南京邮电大学电子科学与工程学院,江苏南京210023

出　　处：《南京邮电大学学报（自然科学版）》2017年第1期90-96,共7页Journal of Nanjing University of Posts and Telecommunications：Natural Science Edition

基　　金：江苏省自然科学基金(BK20130880);江苏省高校自然科学基金(14JB510025)资助项目

摘　　要：提出了一种低功耗的可编程分频器,包括相位切换型预分频器和可编程计数器,将相位切换预分频器中的相位选择器和二分频器组成套叠结构,降低了互连损耗和失配,省去了缓冲器以及二分频器的功耗,实现了一种低功耗的相位切换预分频器。将程序计数器和脉冲吞咽计数器中D触发器进行共用,使计数器中D触发器的总数减少了一半,降低了可编程计数器的面积和功耗。采用SMIC 0.18μm CMOS工艺实现了相位选择器与二分频电路,并将之集成于4.8 GHz频段锁相环频率综合器中,工作频率为4.64~5.40 GHz,在1.8 V电源电压下,分频器消耗电流3 m A,其中相位选择器仅消耗550μA。A low-power programmable divider is proposed, including the phase-switching prescaler and the counter. The phase selector and divide-by-2 circuit are stacked to form a telescopic structure, reduce the interconnection loss and mismatch and allow for a power consumption saving of the buffer and the di- vide-by-2 circuits. A low-power phase-switching prescaler is realized based on the circuit. Besides, the programmable counter and the pulse-swallow counter are designed by reusing their D flip-flops, and the total number of the D flip-flops is reduced, as well as the chip size and the power consumption of the counter. The PLL frequency synthesizer with the proposed divider is designed and fabricated in SMIC 0.18 μm CMOS process for the 4.8 GHz-band. The measured frequency is from 4.64 GHz to 5.4 GHz. The total power consumption of the divider is 3 mA at 1.8 V supply voltage and the current of the phase switching circuit is 550 μA.

关 键 词：相位切换型预分频器 可编程分频器 锁相环频率综合器 

分 类 号：TN453[电子电信—微电子学与固体电子学]