基于FPGA的浮点除法器的研究与实现  

Research and Implementation of Floating-point Divider Based on FPGA

作　　者：钟强[1] 刘鹏飞[1] 刘宝军[1] 胡宗进[1] 秦绪栋[1] 

机构地区：[1]烟台大学,山东烟台264005

出　　处：《中国集成电路》2016年第9期43-46,共4页China lntegrated Circuit

基　　金：烟台大学研究生科技创新基金(基金编号:YDYB1615)

摘　　要：文章针对现场可编程门阵列(FPGA)器件的某些芯片不支持浮点除法运算的情况,设计出一种输出为32位的单精度浮点数的除法器。文章利用已有的整数除法器的IP核(IP Core)进行改进,大大的降低了程序设计的复杂性,并且保证了可靠性。通过Model Sim仿真软件,证明我们设计的算法结果正确,完全满足要求。The article aiming at some chip of field programmable gate array （ FPGA ）device does not support floating- point division operation situation, design a output of 32-bit single precision floating point divider.In this paper the ex- isting integer divider of the IP core was improved, greatly reduces the complexity of the design process, and to ensure the reliability.Through ModelSim simulation software, we have proved that the algorithm is correct, and we have reached our requirements.

关 键 词：浮点 除法器 现场可编程门阵列 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构]