基于SHA-1算法的硬件设计及实现  

Design and implementation of hardware based on SHA-1

作　　者：王文功[1] 于松林[1] 李玉峰[1] 陈博[1] 

机构地区：[1]国家数字交换系统工程技术研究中心,河南郑州450000

出　　处：《电子设计工程》2017年第4期14-17,共4页Electronic Design Engineering

基　　金：国家科技支撑计划(2014BAH30B01);国家自然科学基金创新群体项目(61521003);国家重点基础研究发展规划课题(973计划);基金资助项目(2012CB315901;2013CB329104)

摘　　要：SHA-1(Secure Hash Algorithm)是一种非常流行的安全散列算法,为了满足各种应用对SHA-1算法计算速度的需要,该文围绕Hash函数,基于本课题组的密文取情平台,对SHA-1算法进行深入研究,面向Xilinx K7 410T FPGA芯片设计SHA-1算法实现结构,完成SHA-1算法编程,进行测试和后续应用。该算法在FPGA上实现,可以实现3.2 G bit/s的吞吐率,最大时钟频率为95 MHz。仿真结果表明,与其它硬件设计相比,该算法在不影响原算法的安全的基础上可以获得更高的运行速度和吞吐量。SHA-1 algorithm is the most commonly used secure hash algorithms, in order to meet theneeds of higher operation speed, This paper around the Hash function, based on the research platformfor the cipher text take affection, to conduct the thorough research to the SHA - 1 algorithm, facing theXilinx K7 SHA-1 410 t the FPGA chip design algorithm structure for testing and subsequentapplications. The algorithm on the FPGA implementation, it can implement the throughput of 3.2 G bit/s, maximum clock frequency of 95MHZ. The simulation results show that compared with other hardwaredesign, the algorithm without affecting the safety of the original algorithm on the basis of higher speedand throughput can be obtained.

关 键 词：SHA-1 哈希函数 算法 FPGA 

分 类 号：TN918[电子电信—通信与信息系统]