改进型高速高精度CORDIC算法及其在DDFS中的应用  

Direct Digital Frequency Synthesizer Based on an Improved High Speed&High Precision CORDIC Algorithm

作　　者：史方显 曾立[1] 陈昱[1] 王淼[1] 占丰 

机构地区：[1]北京航空航天大学宇航学院,北京100191 [2]山东航天电子技术研究所,山东烟台264000

出　　处：《电子学报》2017年第2期446-451,共6页Acta Electronica Sinica

基　　金：国家自然科学基金(No.41274190;No.41074130;No.41327802)

摘　　要：提出了一种新的选择迭代式高速高精度CORDIC(COrdinate Rotation Digital Computer)算法.基于表驱动法缩小目标旋转角度,通过改进的基本角度选择方法旁路不必要的迭代;并以移位和减法实现幅度校正,减小硬件资源消耗.设定角度误差小于10^(-5)rad时,迭代次数减小至7次以下.在DDFS(Direct Digital Frequency Synthesizer)的应用中,利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明,该算法幅度误差小于2×10^(-5),输出延时不大于43.5ns,同时硬件资源消耗不增加.A novel optional-iteration high speed and high precision CORDIC algorithm is proposed in this paper.First the rotation is conducted with a corresponding angle based on table-driven method.Then the algorithm bypasses unnecessary iterations using a new basic angle choosing technique.And the correction is achieved by shift and subtraction to reduce hardware consumption.Calculation and simulation indicate that the new algorithm can reduce the iteration number to less than 7 when the phase error is smaller than 10^-5rad.In the application of DDFS,20 fractional binary bits design is implemented in Xilinx FPGA with range reduction method.This design can reduce amplitude error to smaller than 2 × 10^-5 for sine and cosine,cut the output delay down to 43.5ns in circuit test,and no hardware consumption increase.

关 键 词：坐标旋转数字计算机 直接数字频率合成器 表驱动 现场可编程门阵列 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]