基于异构多核可编程系统的大点FFT卷积设计与实现  

Design and implementation of large FFT convolution on heterogeneous multicore programmable system

作　　者：张多利[1] 沈休垒 宋宇鲲[1] 杜高明[1] 

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《电子技术应用》2017年第3期16-20,共5页Application of Electronic Technique

基　　金：国家自然科学基金(61106020)

摘　　要：如今FFT卷积广泛应用于数字信号处理,并且过去几年证实了异构多核可编程系统(HMPS)的发展。另外,HMPS已经成为DSP领域的主流趋势。因此,研究基于HMPS大点FFT卷积的高效地实现显得非常重要。基于重叠相加FFT卷积方法,设计一款针对输入数据流的高效流水重叠相加滤波器。介绍了基于HMPS的大点FFT卷积实现,获得了高精度的滤波效果。此外,采用流水技术的滤波器设计,提高系统处理速度、数据吞吐率和任务并行度。基于Xilinx XC7V2000T FPGA开发板上的实验表明,参与运算的采样点越大,系统的任务并行度、处理速度和数据吞吐率就会越高。当采样点达到1M时,系统的平均任务平行度达到了5.33,消耗了2.745×10~6个系统时钟周期数,并且绝对误差精度达到10^(-4)。Nowadays FFT convolution is widely applied to digital signal processing（DSP）, and the past few years have witnessed the development of the heterogeneous muhicore programmable system （HMPS）. In addition, HMPS has been the mainstream in the field of DSP. So it is very important to study the high efficient implementation of large FFT convolution on the HMPS. In this paper, a high efficient pipelined overlap-add filter based on the overlap-add FFT convolution method is designed for the input streaming data. This paper introduces the implementation of large FFT convolution on the HMPS and achieves the high accuracy of filter re- sult. Furthermore, a pipeline technology is adopted for the filter design to improve processing speed, throughout and parallelism of tasks. The Xilinx XC7V2000T FPGA verification result shows that the larger sampling points are involved in computing, the higher task parallelism, processing speed and throughout will be obtained. When the sample points reach 1M, the system average task par- allelism is 5.33 with 2.745×10^6 clock cycles and the precision of 10^-4.

关 键 词：FFT卷积 重叠相加 算法映射 任务并行度 异构多核 

分 类 号：TN402[电子电信—微电子学与固体电子学]