基于SoC FPGA的千兆以太网接入设计  

Design on Gigabit Ethernet Access Based on SoC FPGA

作　　者：季茂胜[1] 左国辉[1] 张丽娜[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《计算机与网络》2017年第2期94-96,共3页Computer & Network

摘　　要：SoC FPGA作为一种新兴的处理器平台,正在得到广泛的应用。SoC FPGA的硬核处理系统HPS自身包含千兆以太网RGMⅡ接口,同时HPS可通过片内FPGA拓展出千兆以太网接口。为了实现高速IP数据的接入处理,提出了一种基于ALTERA Cyclone V芯片和千兆以太网物理层芯片的设计方案。实验结果表明,该方案可实现多路千兆以太网数据的接入,并对数据进行应用层处理。与其他千兆以太网接入处理电路相比,具有系统集成度高、性能稳定和功耗低的优点,拥有广阔的应用前景。SoC FPGA is wildly used as an emerging processing platfoml. The HPS of SoC FPGA can not only support RGMII interface itself, but also generate RGMII interface through FPGA. To deal with high-speed IP data, a design scheme is proposed based on ALTERA Cyclone V chip and gigabit ethernet PHY chip. The simulation result shows that the system can support multi-channel gigabit ethemet data access, and process the data in the application layer. Compared with other gigabit ethemet access system, the proposed scheme has such advantages as high stability, high integration low power consumption, which has wider application prospect.

关 键 词：SOC FPGA R.GMII 千兆以太网 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术]