高性能阵列重构的SAT描述模型  

Satisfiability-based description model for reconfiguring power efficient VLSI array

作　　者：胡佳[1] 钱俊彦[1] 周志德[1] 

机构地区：[1]桂林电子科技大学计算机与信息安全学院,广西桂林541004

出　　处：《桂林电子科技大学学报》2017年第1期40-43,共4页Journal of Guilin University of Electronic Technology

基　　金：国家自然科学基金(61562015);广西自然科学基金(2015GXNSFDA139038);桂林电子科技大学研究生教育创新计划(YJCXS201537)

摘　　要：为了降低容错处理器阵列的能耗开销,提出一种基于可满足性(SAT)的高性能阵列的可满足性模型。该方法通过结合可满足性的思想,将含故障单元的处理器阵列重构问题转换为关于逻辑列的组合优化问题,并使用布尔逻辑表达式将逻辑列的组合优化表示为高性能阵列的可满足性模型。分析表明,在该可满足性模型的基础上,可通过高效的可满足性求解器快速重构高性能目标阵列。In order to reduce the energy consumption of reconstruction of the fault tolerant processor array,the SAT model of the power efficient VLSI array based on the thought of satisfiability is proposed.And the reconfiguration problem of array contained the faulty processor element is transformed into a combination and optimization problem of logic columns by combining the idea of satisfiability,which is further converted into the SAT model of the power efficient target array by using Boolean expressions.The analysis shows that the power efficient target array can be constructed by high-performance and efficient satisfiability solver with the SAT model of the power efficient target array.

关 键 词：重构 可满足性 超大规模集成处理器阵列 容错 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]