基于FPGA的AES硬件实现及优化  

Implement and optimization of AES using hardware based on FPGA

作　　者：于松林[1] 王文工[1] 陈博[1] 陈祥[1] 张霞[1] 

机构地区：[1]国家数字交换系统工程技术研究中心,河南郑州450002

出　　处：《电子设计工程》2017年第6期75-78,83,共5页Electronic Design Engineering

基　　金：国家科技支撑计划项目(2014BAH30B01);国家自然科学基金创新群体项目(61521003)

摘　　要：AES(Advanced Encryption Standard)是一种非常流行的对称加密算法,字节替换是AES算法中十分重要的部分。针对采用复合域方法来实现字节替换吞吐率小的问题,本文利用先计算的方法进行了5级轮内流水线设计,去除关键路径上的一些计算来降低关键路径延迟提高吞吐率。在FPGA器件Virtex-6 XC6VLX240T上,通过Xilinx ISE 14.7进行仿真实验,结果表明在面积增加相对不大的情况下,提高了吞吐率以及吞吐率/面积比。AES （Advanced Encryption Standard） is a very popular symmetric encryption algorithm. Byte substitution （S-Box）is an important part in AES. However, S-Box which uses the method of the composite field to implement suffers from extremely low throughput rate. In this paper, a 5-stage pipelined structure, by applying pre-computation can be eliminated so as to reduce the critical path the ratio of data throughout and area is increased at method, some computation on the critical data path delay. The results show that the throughput rate and the expense of a fairly modest increase in area.

关 键 词：AES 字节替换 复合域 先计算方法 

分 类 号：TN918[电子电信—通信与信息系统]