JESD204B协议中自同步加解扰电路设计与实现  

Implementation and design of self-synchronous scrambling and descrambling circuit based on JESD204B standard

作　　者：欧阳靖[1] 姚亚峰[1] 霍兴华[1] 谭宇[1] 

机构地区：[1]中国地质大学机械与电子信息学院,湖北武汉430074

出　　处：《电子设计工程》2017年第7期148-151,共4页Electronic Design Engineering

摘　　要：作为JEDEC最新修订的AD/DA串行传输协议,JESD204B采用自同步扰码对数据链路层原始信号进行随机化转换,有效地避免了杂散频谱产生,减少了物理层误码概率。本文基于经典状态机结构对JESD204B协议中自同步加扰及解扰电路进行设计实现,文章阐述了协议中自同步扰码的原理细节,提出了一种加扰与解扰状态电路的设计方案,最终对该方案进行实现、仿真与综合。仿真与综合结果表明该方案充分兼容协议控制信号,功能完全符合协议要求,增强了加解扰电路的稳定性与容错性,同时提高了电路的处理效率,可应用于JESD204B高速串行接口电路设计中。As a latest version of AD/DA serial transmission standard proposed by JEDEC, JESD204B uses self-synchronous scrambling to randomize the signal of the data-link layer, which is able to effectively reduce the emergence of spurious spectrums, and hence decreases possibility of bit-error. This article is aimed to using the structure of classic state-machine to design the scrambler and deserambler circuit of JESD204B Standard. The article elaborates the principle of the self-synchronous-scrambling in JESD204B standard at first, then proposes a design scheme of the scrambler and descrambler circuit, finally realizes the design and provides simulation and synthesis results The simulation result proves that this design is completely conform to the standard and enhances the stability of the circuit, in this point, it can be applied in high-speed interface circuit design that specificities in JESD204B.

关 键 词：电路设计 JESD204B协议 加解扰状态电路 

分 类 号：TN46[电子电信—微电子学与固体电子学]