一种高能效的结构不对称指令缓存  

An energy-efficient instruction cache:A symmetric instruction cache

作　　者：刘骁[1] 高红光[1] 陈芳园[1] 丁亚军[1] 

机构地区：[1]江南计算技术研究所,无锡江苏214083

出　　处：《计算机工程与科学》2017年第3期443-450,共8页Computer Engineering & Science

基　　金：国家863计划(2015AA01A301);国家"核高基"重大专项(2013ZX01028001001001)

摘　　要：在现代微处理器中,指令缓存的Tag读取、比较消耗了指令缓存较大比例的能耗。提出一种基于推断的低能耗指令缓存:不对称指令缓存。根据跳转指令比例低的特点,在该结构中区别处理跳转指令和顺序指令,使用和数据不完全对应的简化标记管理位。该结构采用了命中推断和变长指令取指两种创新技术,其中基于命中推断技术解决了指令缓存命中时Tag比较过多的问题;使用变长指令取指技术提高了顺序指令块的命中率。实验结果表明,对于选取的SPEC2006测试程序,不对称指令缓存结构较常规L1指令Cache取指能耗下降了40%~60%,比无标记指令缓存结构TH IC能耗降低了9%;取指ED2P方面,较常规L1指令Cache优化约50%,比TH IC结构优化约17%。Tag access and comparison consumes a significant portion of instruction cachets energy. We propose a power-efficient instruction cache based on inference, asymmetric instruction cache. Se- quential instructions and non-sequential instructions are treated differently and asymmetric ID invalid bits are applied according to lower ration feature of non-sequential instructions. Hit inference technique is used to reduce the number of tag comparison in cache. And adaptive-length instruction fetch tech- niques are designed to reduce the miss rate of sequential instruction blocks. Compared with tagless hit instruction cache （TH IC）, both energy efficiency and performance of the proposed method are im- proved. Experimental results show that the overall energy consumption is reduced by 40%-60% over L1 Cache for most of the selected SPEC2006 benchmarks. Energy-delay2 product （ED2P） of instruction fetch is 50% lower than that of L1 cache and 17% lower than that of TH IC.

关 键 词：能耗 指令缓存 能耗性能积 命中推断 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]