高性能LDPC编码器IP核设计与验证  

Design and Verification of High-performance LDPC Encoder IP Core

作　　者：刘艳欢 崔文朋 张一山[1] 朱曦阳 郑哲 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]全球能源互联网研究院信息与通信研究所,北京102211

出　　处：《微电子学与计算机》2017年第4期8-12,共5页Microelectronics & Computer

基　　金：国家电网公司科技项目(SGRIDGKJ[2013]209号)

摘　　要：为了实现大数据时代以固态硬盘为代表的大容量高吞吐率存储器的纠错编码,基于数学特性优异的LDPC码,提出了一种半并行的LDPC编码器架构.采用SIMD指令的调度控制流方式实现了RU编码算法,完成了码率和码长等参数可动态配置的LDPC编码器的电路设计.通过Matlab与ModelSim联合仿真,并在Xilinx FPGA平台上验证了编码器的功能正确性.结果表明:工作频率为100 MHz时,配置时间少于7μs且相对于其它编码器结构可以在较少的资源下吞吐率可达4.82Gb/s.A semi-parallel LDPC encoder architecture was proposed for Error correction coding used in a solid state hard drive （SSD） which is the representative of large capacity and high throughput memory based on the mathematical characteristics of excellent LDPC codes. Then SIMI） instruction scheduling control flow approach was applied to achieve the RU coding algorithm; LDPC encoder whose parameters such as bit rate and code length were dynamically configurable was designed. The correctness of the encoder was verified through Xilinx FPGA platform and co-simulation of Matlab and ModelSim; Tests showed that configuration time was less than 7 us and the encoder achieved a throughput of 4. 82 Gb/s using fewer resources compared with other encoders when the operating frequency is 100 MHZ.

关 键 词：LDPC 动态配置 编码器 固态硬盘 

分 类 号：TN432[电子电信—微电子学与固体电子学]