Fast Implementation for the Singular Value and Eigenvalue Decomposition Based on FPGA  

作　　者：ZHANG Shuiping TIAN Xin XIONG Chengyi TIAN Jinwen MING Delie 

机构地区：[1]School of Computer Science and Engineering, Wuhan Institute of Technology [2]School of Electronic Information, Wuhan University [3]School of Electronic and Information Engineering, South-central University for Nationalities [4]School of Automation, Huazhong University of Science and Technology

出　　处：《Chinese Journal of Electronics》2017年第1期132-136,共5页电子学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61273279,No.61471400,No.61102064,No.61273241)

摘　　要：A fast and efficient hardware implementation for computing the Singular value decomposition(SVD) and Eigenvalue decomposition(EVD) is presented.Considering that the SVD and EVD are complex and expensive operations, to achieve high performance with low computing complexity, our approach takes full advantage of the combination of parallel and sequential computation, which can increase efficiently the hardware utilization. Besides, regarding to EVD, we propose a hardware solution of a simplified Coordinate rotation digital computer(CORDIC)-like algorithm which can obtain higher speed. The performance analysis and comparison results show that the proposed methods can be realized on Filedprogrammable gate arrays(FPGAs) with less computation time by using systolic array. It will be shown that the proposed implementation could be an efficient alternative for real-time applications.A fast and efficient hardware implementation for computing the Singular value decomposition（SVD） and Eigenvalue decomposition（EVD） is presented.Considering that the SVD and EVD are complex and expensive operations, to achieve high performance with low computing complexity, our approach takes full advantage of the combination of parallel and sequential computation, which can increase efficiently the hardware utilization. Besides, regarding to EVD, we propose a hardware solution of a simplified Coordinate rotation digital computer（CORDIC）-like algorithm which can obtain higher speed. The performance analysis and comparison results show that the proposed methods can be realized on Filedprogrammable gate arrays（FPGAs） with less computation time by using systolic array. It will be shown that the proposed implementation could be an efficient alternative for real-time applications.

关 键 词：SVD EVD Jacobi CORDIC FPGA 

分 类 号：TN791[电子电信—电路与系统]