基于FPGA的CIC滤波器的优化设计  

Optimization Design of CIC Filter Based on FPGA

作　　者：李怡琳[1] 肖顺文[1] 易欢[1] 杨湲 

机构地区：[1]西华师范大学电子信息工程学院,四川南充637009

出　　处：《西华师范大学学报（自然科学版）》2017年第1期106-110,共5页Journal of China West Normal University(Natural Sciences)

基　　金：四川省教育厅科研基金重点项目(15ZA0145)

摘　　要：针对在数字下变频系统中单独应用CIC滤波器实现抽取滤波时,因高阶CIC滤波器通带衰减过大的问题,在原有的CIC滤波器后级联一补偿滤波器以达到降低采样率,防止频率混叠的目的。仿真结果表明,改进后的CIC滤波器通带波纹数减少,通带衰减降幅明显。This paper talks about the problem of large passband attenuation caused by the high order of CIC filter when it is individually applied in the DDC system to achieve decimation and filtration. Because of that,a compensation filter is attached to the original CIC filter to reduce the sampling rate and avoid aliasing frequency. The simulation results show that the improved CIC filter has much fewer ripples and the passband attenuation is obviously decreased.

关 键 词：FPGA 数字下变频 CIC滤波器 ISOP滤波器 

分 类 号：TN92[电子电信—通信与信息系统]