应用于14位流水线ADC的高精度比较器电路设计  

Designing a high precision comparator for 14-bit pipelined ADC

作　　者：徐韦佳 田俊杰[1] 李延标[1] 

机构地区：[1]中国人民解放军理工大学理学院,江苏南京211101

出　　处：《微型机与应用》2017年第6期33-36,共4页Microcomputer & Its Applications

摘　　要：为了实现高性能的流水线ADC,设计了一种应用于流水线14位ADC的高精度CMOS比较器,采用全差分结构的前置放大电路、两级动态latch锁存电路和输出缓冲电路,具有高精度和低功耗的特点。前置差分预放大电路放大输入差分信号,提高了比较器的精度,其本身的隔离作用使比较器具有较小的回踢噪声和输入失调电压;两级正反馈latch结构有效提高了比较器的速度;反相器级联的输出缓冲级电路调整输出波形,增加驱动能力。采用TSMC 0.18μm CMOS工艺,工作于1.8 V电源电压、100 MHz频率,仿真结果显示,该比较器最小分辨电压是3.99 m V,精度达到9位,失调电压为16.235 m V,传输延时为0.73ns,静态功耗为2.216 m W,已成功应用于14位的流水线ADC。In order to achieve high performance pipelined ADC,a precision CMOS comparator applied to 14-bit pipelined ADC is introduced.Preamp circuit of a fully differential structure,two dynamic latch circuit and output buffer circuit are used,and the comparator is characterized by high precision and low power consumption. The differential preamplifier amplifies the input signal and improves the accuracy of the comparator. Its isolation effect makes the comparator with low kickback noise and low input offset voltage. The two positive feedback latch structure effectively improves the speed of the comparator. Cascade inverter output buffer stage circuit adjusts the output waveform and increases driving capability. Using TSMC 0. 18 μm CMOS process,working in a 1. 8 V supply voltage,with frequencies up to 100 MHz,the simulation results show that the minimum resolution voltage is 3. 99 m V,accuracy reaches nine,offset voltage is 16. 235 m V,transmission delay is 0. 73 ns,and static power consumption is 2. 216 m W. Therefore,the precision comparator has been successfully applied to 14 bit pipelined ADC.

关 键 词：比较器 高精度 正反馈 失调 

分 类 号：TN432[电子电信—微电子学与固体电子学]