Cu/SiO_2结构单元在阻变效应中形成导电通道的模型分析  

Analysis of a Model for Conducting Path Formation in Resistive Switching of Cu/SiO_2 Memory Cells

作　　者：罗劲明[1] 

机构地区：[1]嘉应学院物理与光信息科技学院,梅州514015

出　　处：《科学技术与工程》2017年第9期103-106,共4页Science Technology and Engineering

基　　金：广东省自然科学基金博士科研启动项目(2014A030310410)资助

摘　　要：通过建立一个模型,简单地讨论了Cu/SiO_2结构单元在阻变效应中形成导电通道的临界电压特性。该模型考虑了Cu离子在SiO_2薄膜的迁移扩散和Cu离子在薄膜内引起的空间电荷效应,同时考虑了电子电导机制。模型的计算表明,薄膜的结构参数(厚度、电极功函数、掺杂等)对导电通道的形成过程有很大的影响,其临界电压随薄膜厚度和电极功函数的增加而增大,而随Cu离子掺杂浓度增大而减小。这一结果对未来存储器件的性能设计和制造具有一定的指导意义。The critical voltage of conducting path formation before resistive switching in Cu/SiO_2memory cells has been discussed based on a dynamic model,which combines the transition of Cu ions with the space-charge effect,as well as the electric current conduction. The calculations demonstrate that the formation of conducting path depends on the memory cell parameters,that is,the critical voltage increases with the thickness of oxide films and the work function of electrodes,but decreases with the increasing doping concentration of Cu ions. This result would be feasible for circuit design and manufacturing of memory device in future.

关 键 词：SIO2 导电通道 阻变 击穿 

分 类 号：O484.3[理学—固体物理]