MPEG-4并行零树编码电路设计  

A PARALLEL MPEG-4 ZEROTREE ENCODER

作　　者：许超[1] 石青云[1] 

机构地区：[1]北京大学视觉与听觉信息处理国家重点实验室,北京100871

出　　处：《广西师范大学学报（自然科学版）》2003年第A01期169-172,共4页Journal of Guangxi Normal University:Natural Science Edition

摘　　要：设计了一种并行的高效MPEG-4零树编码电路.零树编码由于多位平面串行处理的性质,对实时实现是一个较大的挑战.通过巧妙的预处理电路设计,通过简捷的比特或操作和比特非与操作,保证各位平面的独立编码.对于N个位平面的并行处理,编码速度提高N倍量级.另外,编码电路中全新的递归处理的去除,大系数跳过处理的简化以及按优先级顺序竞争输出,使整体电路的资源使用相对于单个编码电路的增加少于N倍.而且,可以完全保证MPEG-4零树编码方案的性能.本文电路在FPGA集成电路平台上进行了验证.In this paper,a parallel hardware architecture of zerotree coding for MPEG4 texture coding is presented to meet real time processing requirement in video compression.A preprocessing unit of wavelet coefficients is designed to ensure the independent and parallel coding in each bitplane through bitor and bitnotand logic circuits.In zerotree encoder,the recursive scanning of parent and children coefficients is avoided,and skipping processing of significant coefficients is simplified,as well as coded data are output according to priority order.It achieved an increase N times in speed,while less than N times in resource.The architecture is implemented in a platform with FPGA chips.

关 键 词：MPEG-4 零树编码 硬件电路 并行处理 

分 类 号：TN919.81[电子电信—通信与信息系统]