基于全流程并行加速的改进数字下变频器设计  

Design of Improved High-Speed Digital Downconverter Based on Full Poly-phase Parallel Acceleration

作　　者：吉炜寰[1] 邹玉炜[2] 黄磊[3] 

机构地区：[1]河南职业技术学院电气工程系,郑州450046 [2]安阳师范学院物理与电气工程学院,河南安阳455000 [3]东南大学电气工程学院,南京210096

出　　处：《电子器件》2017年第1期142-146,共5页Chinese Journal of Electron Devices

基　　金：国家青年基金项目(51407027);河南省科技厅科技计划项目(142102210517)

摘　　要：针对宽带通信雷达探测系统中高速率数据处理难度较大的问题,设计了一种全流程并行化处理的高速率数字下变频器,混频模块采用并行化的流水线坐标旋转数字计算机(CORDIC)对来自A/D的高速采样数据进行分组处理,以降低单个通道的数据率;抽取滤波模块采用多相滤波器进一步将高阶卷积网络进行并行化分解,减少不必要的乘累加运算。实验结果表明:最大处理速率由原先的131 MHz提高到了255 MHz,改进设计利用现有硬件条件大幅度提高了处理速度,减少了通带内信号的衰减。Aiming to overcome challenge of high-speed data processing in broadband communication radar detection system,a full parallel accelerating computation based digital downconverter is proposed. Mixing module adopts pipelined coordinate rotation digital computer（ CORDIC ）to realize parallel processing of A/D dataflow, which can reduce data rate in single channel. Extraction module adopts poly-phase filter to decompose high-order convolution network,which can reduce unnecessary accumulative operation. The experiment result shows that the maximum working frequency increases from 131 MHz to 255 MHz,and the improved design can effectively improve processing speed and reduce channel attenuation under existing hardware conditions.

关 键 词：数字下变频器 坐标旋转数字式计算机 多相分解 抽取滤波 

分 类 号：TN45[电子电信—微电子学与固体电子学]