一种用于无线收发机的11 bit 150 MS/s Sub-range SAR ADC IP  

An 11 bit 150 MS/s Sub-range SAR ADC IP for Wireless Transceiver

作　　者：何秀菊[1] 薛春莹[1] 王亚[1] 李福乐[1] 张春[1] 姜学平 

机构地区：[1]清华大学微电子所,北京100084 [2]全球能源互联网研究院,北京102211

出　　处：《微电子学与计算机》2017年第5期1-5,11,共6页Microelectronics & Computer

基　　金：国家电网公司科技项目(SGRIDGKJ[2014]156号)

摘　　要：提出一个用于无线收发机的双通道11bit 150 MS/s逐次逼近型(SAR)模数转换器(ADC).ADC的两通道都采用Sub-range SAR的结构,电路中使用自举开关采样,提高电路的线性度;采用全动态比较器,以节省功耗;使用基于等效门控环形振荡器的异步高速SAR逻辑,提高ADC的转换速度.此外,在CDAC中采用分裂电容设计以避免使用导通性不良的中间电压连接开关.本设计在Smic 55nm Low-Leakage CMOS工艺下流片.IP总面积是0.3mm^2,核的有效面积是0.046mm^2.测试结果为:在供电电压和参考电压为1.2V,采样率为150 MS/s的情况下,单通道消耗2.04mA的电流,SNDR为60.9dB,FOM值为17.9fJ/conv.-step.静态特性DNL和INL分别为+0.99/–0.81LSB和+2.21/–1.37LSB.An 11 bit 150 MS/s dual-channel successive-approximation-register （SAR） analog-to-digital converter （ADC） IP for wireless transceiver is presented in this paper. Each channel adopts sub-range SAR architecture, which combines bootstrap switches for high linearity, gate-controlled ring oscillator （GCRO） for high speed and dynamic comparator for low power. In addition, division in Capacitive Digitabto-analog Converter （CDAC） avoids capacitors connecting to common-mode voltage （VCM） and the switch transistors incompletely switching on. The 11 bit 150 MS/s prototype is fabricated in smic 55 nm low leakage CMOS process. The active area of dual-channel ADC IP is 0. 35 mm2, while the core area is 0. 046 rnm2. A single channel consumes 2.04 mA current and achieves an SNDR of 60. 9 dB at 150 MS/s sample rate and 1. 2V supply and reference, resulting in a FOM of 17. 9 fJ/ Conversion-step. Measured DNL and INL are ＋0.99/- 0.81 LSB and ＋2. 21/- 1.37 LSB, respectively.

关 键 词：模数转换器 sub-range SAR 自举开关 低功耗 

分 类 号：TN45[电子电信—微电子学与固体电子学]