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作 者:尹勇生[1] 吴景生[1] 陈红梅[1] 李琨[1]
机构地区:[1]合肥工业大学微电子设计研究所,安徽合肥230009
出 处:《电子技术应用》2017年第5期44-47,共4页Application of Electronic Technique
摘 要:提出了一种带参考注入信号的校准算法,用于校准时间交织模数转换器(Time-Interleaved Analog-to-Digital Converter,TIADC)的时间失配误差。该算法引入参考注入信号,参考注入信号通过采样保持电路(sample hold circuit,S/H)后,利用TIADC的各子通道时钟依次控制S/H,对其输出后的值进行运算获得时间误差,再将时间误差反馈回多相时钟产生器,利用可变延迟线实现时间失配的补偿。该算法运算简单,消耗的硬件资源低,对输入信号没有限制,可以扩展到任意通道。算法应用于一个4通道12 bits的TIADC,当输入信号的归一化频率f_(in)/f_s=0.485 0,设定的最大误差为1.0% T_s时,MATLAB仿真结果表明,经过本算法校准后的SFDR从31.009 4 dB提高到了95.627 0 dB,SNDR从31.074 9 dB提高到了73.480 5 dB,证明了该校准方案的有效性。A calibration algorithm with a reference-injection single was presented in this paper to calibrate the timing mismatch of Time-Interleaved Analog-to-Digital Converter(TIADC). This algorithm used a reference-injection single ,which is sampled by the sub-channal's CLKs of TIADC. We can acquire the timing skew by the operations of the output of the S/H and then feed it back to the muhiphase clk. Achieve the compensation of time-skew with variable delay line. The presented calibration algorithm has lower hardware consumption with no restriction on the input single, and could be extended to arbitrary number of channels. Simulation result of 4 channal 12 bits TIADC with MATLAB shows that, with this calibration algorithm, the SFDR rose from 31.009 4 dB to 95.627 0 dB and the SNDR rose from 31.074 9 dB to 73.480 5 dB at the input frequency fin/fs=0.485 ,was proofed enough the effectiveness of this algorithm.
关 键 词:参考注入信号 时间交织模数转换器 时间失配 可变延迟线
分 类 号:TN432.1[电子电信—微电子学与固体电子学]
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