基于锁相环的高速示波器等效采样系统设计  

Design of equivalent sampling system for high-speed oscilloscope based on PLL

作　　者：查添翼 陈晟祺 戈浚尧 

机构地区：[1]江苏省常熟中学,江苏苏州215500 [2]清华大学电机工程与应用电子技术系,北京100084 [3]南京邮电大学通信与信息工程学院,江苏南京210023

出　　处：《电子技术应用》2017年第5期94-97,共4页Application of Electronic Technique

摘　　要：采用小数分频锁相环芯片ADF4351作为采样时钟发生器,利用FPGA进行等精度测频,运用差频法顺序等效采样原理,设计了最高等效采样率为160 GS/s的高速示波器等效采样系统。同时通过时钟分配器和数字延迟线产生交替采样时钟,利用4片最高采样率为250 MS/s的8 bit ADC进行时间交替采样,使系统的最高实时采样率达到1 GS/s。由于采用低抖动的时钟源,系统在DC到500 MHz的设计带宽内保持了良好的噪声性能,信噪比优于基于DDS技术的等效采样系统。Using the fractional-N PLL chip ADF4351 as the sampling clock generator and FPGA for identical precision frequency measurement, an equivalent sampling system which has a maximum equivalent sampling rate of 160 GS/s is designed for high- speed oscilloscope under the beat frequency method sequential sampling principle. Combining the clock divider with the digital delay line to produce alternating sampling clock, and using four 8-bit ADC to finish time-interleaved sampling, this system＇s highest real-time sampling rate reached 1 GS/s. Due to the low jitter clock source, the system keeps low noise over the designed band- width of DC to 500 MHz, whose signal to noise ratio is better than that of the equivalent sampling system based on DDS.

关 键 词：小数分频锁相环 等效采样 时间交替采样 高速示波器 

分 类 号：TN911.8[电子电信—通信与信息系统] TM935.38[电子电信—信息与通信工程]