基于脉动阵列的HEVC 8×8整数DCT变换的设计与实现  

Design and implementation of HEVC 8×8 integer DCT based on systolic array

作　　者：潘苏文[1] 叶宇煌[1] 郑明魁[1] 陈志峰[1] 杨秀芝[1] Pan Suwen Ye Yuhuang Zheng Mingkui Chen Zhifeng Yang Xiuzhi(School of Physics and Information Engineering, Fuzhou University,Fuzhou 350116, China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350116

出　　处：《微型机与应用》2017年第9期53-56,59,共5页Microcomputer & Its Applications

基　　金：福建省科技重大专项基金资助项目(2014HZ0003-3);福建省自然科学基金资助项目(2015J01251);福建省教育厅项目(JA14065);福州市科技项目计划资助(2015-G-61)

摘　　要：文章基于脉动阵列实现HEVC(High Efficiency Video Coding)中8×8的整数DCT(Discrete Cosine Transform)变换,改进通常使用的蝶型算法。整体架构基于脉动阵列的思想,并采用中间值数据重组的设计,使得变换模块可同时实现行列变换操作。只需得到列变换的第一个值便可开始行变换,充分利用了PE单元,减少变换时间并提高计算模块的并行性。文中方法不仅适用于DCT变换,也可用于其他的8×8矩阵相乘,具有通用性。综合结果表明,该设计最高可工作在203.8 MHz的频率上,与其他算法相比时间上只需35个周期,且资源消耗较少。文中方法非常适合于HEVC视频编码对实时性的要求,为HEVC编码标准的硬件实现提供了参考。In this paper,based on systolic array to achieve the HEVC （ High Efficiency Video Coding） 8× 8 integer DCT transform,and to im -prove the commonly used butterf ly algorithm. The overall architecture based on the thought of systolic array can achieve row and column trans-form synchronization operat ion, make fulluse of PE cells,reduce the conversion time and improve the parallelism of FPGA. The designed ar-chitecture is not only suitable for DCT transform,but also can be used for any 8x8 matrix multip） lication. Finaiy the synthetical results show that this design can work in the highest frequency of 213. 8 MH z. Compared with other algorithms only 35 cycles of time,and less resource cost. The algorithm is very suitable for the real-time requirement of HEVC video image co d in g, provides a reference for hardware implementation of HEVC encoding standard.

关 键 词：高效率视频编码 离散余弦变换 FPGA 脉动阵列 

分 类 号：TN919.81[电子电信—通信与信息系统]