Gzip压缩的硬件加速电路设计  

Hardware-Accelerated Circuit Design for Gzip Compression

作　　者：李冰[1] 王超凡[1] 顾巍[1] 董乾[1] 

机构地区：[1]东南大学集成电路学院,江苏南京210096

出　　处：《电子学报》2017年第3期540-545,共6页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61571116)

摘　　要：硬件无损压缩技术可以发挥专用电路的速度和功耗优势,被广泛应用于大数据计算以及通信领域.本文以GNUzip(Gzip)数据无损压缩技术为原型设计了一种硬件压缩电路.通过采用双Hash函数、并行匹配处理、面向硬件存储的LZ77压缩存储格式、高效数据拼接器等加速方法,发挥并行计算和流水线结构优势,提升压缩速率.该硬件压缩电路基于Verilog HDL设计,使用现场可编程门阵列(FPGA)进行测试和验证.测试数据表明:与软件压缩方式相比,该硬件压缩电路在获得适中压缩率(65.9%)的同时,其压缩速率得到显著提升,平均压缩速率达171Mb/s,满足网络通信、数据存储等实时压缩应用需求.The hardware implementation of lossless data compression is wildly used in big data computing and com- munication, since it combines the speed and power advantage of the dedicated circuit. This paper proposed a hardware com- pression circuit based on GNUzip（Gzip） lossless data compression algorithm. The dual Hash functions, parallel match pro- cessing,hardware storage oriented LZ77 compression data format and high-performance data adaptor were involved to accel- erate the compression speed with the advantages of parallel calculation and pipeline structure. The hardware compression cir- cuit,based on Verilog HDL, was tested and verified by field programmable gate array （FPGA）. The test data shows that, compared with software implementation, the compression speed of hardware circuit is improved significantly while the com- pression rate is 65.9%. The average speed is up to 171Mb/s that can satisfy the real-dine compression requests of network communication and data storage.

关 键 词：无损压缩 GZIP 硬件 LZ77 FPGA 

分 类 号：TP391.1[自动化与计算机技术—计算机应用技术] TN492[自动化与计算机技术—计算机科学与技术]