2.488 Gbit/s时钟数据恢复电路的设计  

Design of a 2.488 Gbit/s Clock and Data Recovery Circuit

作　　者：杨丽燕[1] 刘亚荣[1] 王永杰[1] 

机构地区：[1]桂林理工大学信息科学与工程学院,广西桂林541004

出　　处：《半导体技术》2017年第5期340-346,357,共8页Semiconductor Technology

基　　金：桂林理工大学"嵌入式技术与智能信息处理"广西高校重点实验室2016-2017年度基金资助项目(2016-02-08)

摘　　要：利用Cadence集成电路设计软件,基于SMIC 0.18μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路。该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换。整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成。后仿真结果表明,系统电源电压为1.8 V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566μm×448μm。A 2. 488 Gbit/s third-order charge pump phase locked loop type clock and data recovery （CDR） circuit was designed by the Cadence integrated circuit design soft ware and based on the SMIC 0. 18 p,m 1P6M CMOS process. The design of the CDR circuit was realized by a dual-loop structure. In order to increase the capture range of the whole loop and reduce the locking time, a reference clock auxiliary frequency locked loop was added to the phase locked loop （PLL）. The real-time monitoring of the frequency error by the locked detection loop was carried out to achieve dual-loop switching. And the whole circuit was composed of a phase detector, a phase frequency detector, the charge pumps, a loop filter and a voltage controlled oscillator. The post-simulation results show that when the system power supply voltage is 1.8 V and the non-return-to-zero （NRZ） code input data is 2. 488 Gbit/s, the jitter peak of the recovery data is 14.6 ps, the locking time is 1.5 μs and the power consumption is 60 mW. The layout of core circuits covers an area of 566 μm ×448 μm.

关 键 词：时钟数据恢复(CDR)电路 双环路结构 锁相环(PLL) 压控振荡器(VCO) 相位抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN710