SM3杂凑算法的SoPC组件实现  

Implementation of SM3 algorithm based on SoPC component

作　　者：邵梦丽 殷新春[1,2] 李艳梅[1] SHAO Meng-li YIN Xin-chun LI Yan-mei(School of Information Engineering,Yangzhou University, Yangzhou 225000, China School of Guangling, Yangzhou University, Yangzhou 225000, China)

机构地区：[1]扬州大学信息工程学院,江苏扬州225000 [2]扬州大学广陵学院,江苏扬州225000

出　　处：《网络与信息安全学报》2017年第5期47-53,共7页Chinese Journal of Network and Information Security

基　　金：国家自然科学基金资助项目(No.61472343);江苏省普通高校研究生科研创新计划项目(No.KYLX15_1362)~~

摘　　要：首先给出了SM3在SoC上的实现,然后主要分析了算法的结构,选择Verilog语言进行算法描述,使用Model Sim进行仿真,用SoPC Builder进行接口封装,最后在Cyclone IV系列的EP4CE22F17C8N上进行了实现,测试表明,运行频率可以达165 MHz,吞吐量为1 184.8 Mbit/s。Firstly the realization of SM3 on SoC was given. The structure of the algorithm was analyzed mainly, and the algorithm was realized by the Verilog hardware description language, in order to simulate this algorithm, the A1- tera simulation software ModelSim was chosen, SoPC Builder was used for interface package, and finally it was im- plemented in the Cyclone IV EP4CE22F17C8N. Its operation frequency can reach 165 MHz and its throughput rate is 1 184.8 Mbit/s.

关 键 词：SM3 FPGA 硬件实现 SOC 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]