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作 者:孟凡振[1,2] 刘宏[1] 汪明亮[1] 林水样 田彤[1,2]
机构地区:[1]中国科学院上海微系统与信息技术研究所,上海201801 [2]中国科学院大学电子电气与通信工程学院,北京100049
出 处:《西安电子科技大学学报》2017年第3期108-113,共6页Journal of Xidian University
基 金:国家科技重大专项资助项目(2013ZX03001017-002);上海市经信委科技攻关专项资助项目(13XI-32)
摘 要:为了解决物联网无线通信中成本和功耗的问题,设计了一种带滤波功能的互补金属氧化物半导体低功耗欠采样器.基于欠采样原理利用高采样比时钟信号完成无源欠采样变频,并利用采样开关和电容级联巴伦低噪声放大器输出并联谐振负载形成带通滤波器,有效地降低了折叠噪声,改善了噪声系数.同时集成巴伦低噪声放大器代替片外巴伦产生差分信号,从而实现了系统高集成度和低功耗.针对物联网无线通信的应用,该欠采样器采用联华电子公司的65nm互补金属氧化物半导体工艺进行仿真设计.结果表明,当射频中心频率为780MHz时,该欠采样器能够在输入幅度为-90dBm情况下利用41MHz采样频率变频,实现较高的采样比和较好的带外抑制,并且在1.2V电源电压下,欠采样器电流消耗为1.6mA.此外,该欠采样器可根据不同的射频信号频率,选择合适的采样频率,灵活地实现频率变换.To solve cost and power consumption problems of wireless communication of the internet of things (IoT), a CMOS low power sub-sampler with filtering is proposed. Based on the subsampling theory, the subsampler adopts the clock signal with the high sampling ratio to achieve the passive subsampling mixer. It incorporates the sampling switches and capacitors directly into the parallel resonant output load of the balun low noise amplifier (balun-LNA) to form the bandpass filter, which reduces noise folding to improve the noise figure. And with the integrated balun-LNA instead of the off-chip balun it generates the differential signal, which achieves high integration and low power consumption of the system. For the application of loT wireless communication, the sub-sampler is implemented and simulated based in the UMC 65 nm CMOS process. The results show that it can achieve the subsarnpling frequency down-conversion at the sensitivity of --90 dBm by using the clock sampling frequency of 41 MHz operating at the central frequency of 780 MHz, which acquires a high sampling ratio and better out-band rejection, and its current consumption is 1.6 mA at the 1.2 V voltage supply. In addition, the proposed sub-sampler chooses the proper sampling frequency to achieve the frequency conversion flexibly, based on different RF signal frequencies.
分 类 号:TN773.1[电子电信—电路与系统]
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