一种面向雷达应用可重构系统中的数据缓存结构和管理机制  

Data Memory Structure and Management Strategy of Reconfigurable System for Radar

作　　者：刘波[1] 王晓彤[1] 张冬明[1] 葛伟琪[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《上海交通大学学报》2017年第5期628-635,共8页Journal of Shanghai Jiaotong University

基　　金：国家自然科学基金项目(61404028;61204023);国家高技术研究发展计划(863)项目(2012AA012703)资助

摘　　要：针对面向雷达应用可重构系统中数据访存冲突严重、访存效率低等问题,设计了一种片上层次化缓存结构,并提出基于多存储体的线性步长可变的数据管理机制,通过建立计算阵列与各个存储体之间可配置的逻辑映射关系,有效降低了多个计算阵列并行工作时产生的访存冲突,提高了计算阵列的数据吞吐率,从而提高了可重构系统的数据访存性能.结果表明,该方案在有效控制硬件开销的同时,极大地提升了可重构系统的数据访存性能,以256~64×210快速傅里叶变换为例,与经典并行缓存机制相比,可重构系统的数据访存性能提升了26.09%~54.60%.Aiming at the serious problems of access conflicts and low access efficiency, this paper proposes a hierarchical memory structure and data management strategy based on linear varying step-size for radar sub-algorithms. By establishing the logical mapping strategy between the reconfigurable arrays and the multi-bank memory, our design successfully reduces the access conflicts when the tasks assigned on differ- ent arrays fetch the required data in parallel and achieves a higher throughput. Consequently, the data ac- cess performance of the reconfigurable system is improved. Based on the TSMC 45 nm complementary met- al oxide semiconductor （CMOS） technology, the memory access performance can be increased highly for radar sub-algorithms. An example of the 256-point to 64 × 21-10-point fast Fourier transform （FFT） shows that the performance of the reconfigurable system compared to the representative parallel memory architec- ture （PMA） approach can be improved by 26.09% to 54.60%.

关 键 词：可重构系统 数据缓存结构 数据管理机制 

分 类 号：TN302[电子电信—物理电子学]