基于FPGA的极化码译码研究及实现  

The research and implementation of polarization code decoding based on FPGA

作　　者：邓媛媛[1] 卿粼波[1] 王正勇[1] 高菁汐 徐成强[1] 

机构地区：[1]四川大学电子信息学院,四川成都610064

出　　处：《电子技术应用》2017年第6期37-40,44,共5页Application of Electronic Technique

摘　　要：在二进制离散无记忆信道中极化码可以达到其信道极限容量,并且实现的复杂度较低,这在通信领域无疑是一个重大突破,因此在FPGA中实现极化码的译码有着非常重要的研究意义。首先介绍了SC(Successive Cancellation)译码算法,并将该算法的蝶形结构改进为线形结构从而提高了译码效率;接着对译码算法做了包括最小和译码、定点量化和资源共享的改进,以便于在硬件中更容易实现;最后在FPGA中实现了极化码的译码并给出了测试波形以及对不同编码块长度的综合资源进行了对比。实验结果表明,译码的最高频率可达145 MHz,吞吐率可达36.4 Mbps。In the binary discrete memoryless channel, polarization code can achieve its channel capacity limit and its implementation complexity is relatively low,which is a major breakthrough in communication field,so it is a very important research significance to realize polarization code decoding in FPGA. Firstly, the SC decoding algorithm is introduced and the butterfly structure is converted into liner structure in order to improve the efficiency of decoding. Then the decoding algorithm is improved by minimum decoding, fixed-point quantifying and resources sharing so that it is easier to implement in hardware. Finally, realizes the polarization code decoding in FPGA and gives the test waveforms, while the comprehensive resource about different coding block length are also compared in this paper. The experimental results show that the decoding can reach the highest frequency 134 MHz and reach the throughput rate 35.6 Mbps.

关 键 词：FPGA 极化码 信道极化 SC译码 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]