基于FPGA的高速串行数据收发接口设计  

Design of high-speed serial data transceiver interface based on FPGA

作　　者：刘安[1,2] 禹卫东[1] 马小兵[1] 吕志鹏[1,2] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学电子电气与通信工程学院,北京100039

出　　处：《电子技术应用》2017年第6期48-51,共4页Application of Electronic Technique

摘　　要：针对传统ADC/DAC应用中采样数据并行传输存在线间串扰大、同步难等问题,设计了一种基于高速串行协议——JESD204B的数据收发接口。以Xilinx公司V7系列FPGA为核心控制单元设计电路,在单通道传输速率为6 Gb/s的条件下完成数据收发测试,验证了传输过程中数据的同步性、准确性及整体方案的可行性。设计结果表明,这种串行传输方式不仅解决了并行传输所带来的诸多问题,还降低了制板设计时PCB布线的复杂程度、减少了板层数量、节约了成本。To solve the problems of synchronization and inter-symbol interference caused by parallel transmission, this paper studies the high-speed serial protocol-JESD204B and provides a design of data transceiver interface based on the V7 series FPGA of Xilinx. The experiment is conducted under the bit rate of 6 Gb/s per lane, the test result verifies that this design could fulfill the requirements of synchronization and accuracy during data transmission, and also shows that serial transmission simplifies the layout of PCB, decreases the number of layers and the cost of project, which has more advantages than parallel mode.

关 键 词：高速串行协议 JESD204B 数据传输接口设计 FPGA 模数/数模转换器 

分 类 号：TN911.73[电子电信—通信与信息系统]