HyBar:high efficient barrier synchronization based on a hybrid packet-circuit switching Network-on-Chip  

作　　者：Zhenqi WEI Peilin LIU Rongdi SUN 

机构地区：[1]School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China

出　　处：《Science China(Information Sciences)》2017年第6期233-244,共12页中国科学（信息科学）（英文版）

基　　金：partially supported by Equipment Pre-Research Foundation of China(Grant No.9140A08010414JW03025)

摘　　要：Realizing barrier synchronization in multi-/many-core processors with high efficiency becomes more and more challenging as the number of cores integrated in a single chip keeps growing. Quite a few barrier solutions have been proposed, while they provide limited improvements for synchronizing large amounts of cores or incur unfavorable restrictions on performing concurrent barriers. This paper presents Hy Bar, a hardware barrier based on a hybrid switching No C which adopts packet switching and circuit switching methods in two sub-networks respectively. Dedicated channels in the circuit-switching sub-network are dynamically built and removed when barrier requests traverse the packet-switching sub-network according to a modified dimensionorder routing algorithm. The efficiency of inter-core communication for concurrent barriers is improved by merging barrier arrival requests and broadcasting release requests along the circuit channels. The execution time of synthetic cases, benchmark kernels and parallel applications using various barrier solutions are evaluated in an RTL-based simulation platform. Experimental results show that our proposal provides about 15%–50%performance improvement compared to previous solutions, while the hardware overhead is marginal under SMIC40 nm technology. Moreover, Hy Bar introduces a minor efficiency loss for concurrent barriers with no limitation on their layouts of participating cores in the on-chip network.Realizing barrier synchronization in multi-/many-core processors with high efficiency becomes more and more challenging as the number of cores integrated in a single chip keeps growing. Quite a few barrier solutions have been proposed, while they provide limited improvements for synchronizing large amounts of cores or incur unfavorable restrictions on performing concurrent barriers. This paper presents Hy Bar, a hardware barrier based on a hybrid switching No C which adopts packet switching and circuit switching methods in two sub-networks respectively. Dedicated channels in the circuit-switching sub-network are dynamically built and removed when barrier requests traverse the packet-switching sub-network according to a modified dimensionorder routing algorithm. The efficiency of inter-core communication for concurrent barriers is improved by merging barrier arrival requests and broadcasting release requests along the circuit channels. The execution time of synthetic cases, benchmark kernels and parallel applications using various barrier solutions are evaluated in an RTL-based simulation platform. Experimental results show that our proposal provides about 15%–50%performance improvement compared to previous solutions, while the hardware overhead is marginal under SMIC40 nm technology. Moreover, Hy Bar introduces a minor efficiency loss for concurrent barriers with no limitation on their layouts of participating cores in the on-chip network.

关 键 词：NOC barrier synchronization packet-circuit switching concurrent barriers routing algorithm 

分 类 号：TN47[电子电信—微电子学与固体电子学]