基于多核DSP的雷达对抗侦查仿真机硬件设计与实现  

Hardware design and implementation of radar confrontation and reconnaissance computer based on multicore DSP

作　　者：陈川[1] 王国东[1] 张坤[1] Chen Chuan Wang Guodong Zhang Kun(Xi＇an Aeronautics Computing Technique Research Institute,AVIC,Xi＇an 710065,China)

机构地区：[1]中国航空工业集团公司西安航空计算技术研究所,陕西西安710065

出　　处：《电子技术（上海）》2017年第5期30-32,共3页Electronic Technology

摘　　要：以TI公司的最新型多核DSP TMS320C6678为研究对象,提出一种基于四个多核DSP的雷达对抗侦查仿真机核心模块的硬件设计方法与实现,重点详细介绍了所设计的处理器及其时序要求、时钟电路、复位电路、SRIO交换电路的设计实现方法。该设计能够很好地满足现今日益发展的雷达对抗侦察算法对于信号处理硬件的高性能需求,具有很高的实用价值。Taking the TI company＇s newest multi-core DSP（TMS320C6678） as the research object, This paper presents a hardware design method and implementation of core module of radar reconnaissance simulator based on four multi-core DSP. Then we introduce the design and implementation of the processor, timing, clock circuit, reset circuit and SRIO switching circuit. The design can well meet the high-performance requirements of the growing radar confrontation and reconnaissance algorithm on signal processing hardware. It has a high practical value.

关 键 词：多核DSP TMS320C6678 SRIO UCD9222 CPS1616 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]