High-Throughput Area-Efficient Processor for Cryptography  

作　　者：HUO Yuanhong LIU Dake 

机构地区：[1]School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China [2]School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China

出　　处：《Chinese Journal of Electronics》2017年第3期514-521,共8页电子学报（英文版）

基　　金：supported by the National High-Tech Research and Development Program(863 Program)of China(No.2014AA01A705)

摘　　要：Cryptography circuits for portable electronic devices provide user authentication and secure data communication.These circuits should,achieve high performance,occupy small chip area,and handle several cryptographic algorithms.This paper proposes a highperformance ASIP(Application specific instruction set processor)for five standard cryptographic algorithms including both block ciphers(AES,Camellia,and ARIA)and stream ciphers(ZUC and SNOW 3G).The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption,16.0 Gb/s for ZUC,and 32.0 Gb/s for SNOW3G,etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2(65 nm).Compared with stateof-the-art VLSI designs,our design achieves high performance,low silicon cost,low power consumption,and sufficient programmability.For its programmability,our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use.The product lifetime of our design can thus be extended.Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, achieve high performance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a high-performance ASIP （Application specific instruction set processor） for five standard cryptographic algorithms including both block ciphers （AES, Camellia, and ARIA） and stream ciphers （ZUC and SNOW 3G）. The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm^2 （65 nm）, Compared with state- of-the-art VLSI designs, our design achieves high performance, low silicon cost, low power consumption, and sufficient programmability. For its programmability, our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.

关 键 词：ASIP(Application specific instruction set processor) Cryptographic processor VLSI(Very largescale integration) CRYPTOGRAPHY 

分 类 号：TN918.1[电子电信—通信与信息系统]