一种基于65 nm CMOS工艺的10位10 MS/s SAR ADC  

A 10 bit 10MS/s SAR ADC Based on 65 nm CMOS Process

作　　者：邓红辉[1] 汪江[1] 周福祥[1] 

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009

出　　处：《微电子学》2017年第3期298-303,共6页Microelectronics

基　　金：安徽省科技攻关项目(JZ2014AKKG0430);中央高校基本科研业务费专项资金资助项目(2014HGCH0010)

摘　　要：基于SMIC 65nm CMOS工艺,设计了一种10位10 MS/s逐次逼近型模数转换器(SAR ADC)。采用全差分的R-C组合式DAC网络结构进行设计,提高了共模噪声抑制能力和转换精度。与全电容结构相比,R-C组合式DAC网络结构有效减小了版图面积。DAC中各开关的导通采用对称的开关时序,使比较器差分输入的共模电平保持为固定值,降低了比较器的失调电压,提高了ADC的线性度。在2.5V模拟电源电压和1.2V数字电源电压下,使用Spectre进行仿真验证,测得DNL为0.5LSB,INL为0.8LSB;在输入信号频率为4.990 2 MHz,采样频率为10 MHz的条件下,测得电路的有效位数为9.63位,FOM为0.04pJ/conv。A 10-bit 10 MHz sampling rate successive approximation A/D converter was designed in SMIC 65 nm CMOS process. A fully differential R-C combined DAC network structure was used. The common mode noise rejection capability and the conversion accuracy were improved by the fully differential structure. Compared with the full capacitance structure, the R-C combined DAC network structure could effectively reduce the layout area. The symmetrical switching sequences were used when the DAC＇s switches were working in the conduction operation, which could make the common mode voltage of comparator＇s differential input to be kept in a fixed value, and also could reduce the comparator＇s offset and improve the ADC＇s linearity. With analog power supplies of 2.5 V and digital power supplies of 1.2 V, results from Spectre simulation showed that the maximum differential nonlinearity error was 0.5 LSB, and the maximum integral nonlinearity error was 0.8 LSB. At an input signal frequency of 4. 990 2 MHz and a sampling frequency of 10 MHz, the measured ENOB was up to 9.63 bit, and the FOM was 0.04 pJ/conv.

关 键 词：逐次逼近型ADC R-C组合式DAC网络 对称开关时序 

分 类 号：TN432[电子电信—微电子学与固体电子学]