一种8位1 GS/s折叠内插A/D转换器  

An 8 bit 1 GS/s Folding and Interpolating Analog-to-Digital Converter

作　　者：邓红辉[1] 程海玲[1] 汪江[1] 

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009

出　　处：《微电子学》2017年第3期304-308,共5页Microelectronics

基　　金：中央高校基本科研业务费专项资金资助项目(2014HGCH0010);安徽省科技攻关项目(JZ2014AK KG0430)

摘　　要：基于TSMC 0.18μm CMOS工艺,采用两级级联的折叠内插结构,设计了一种8位1GS/s折叠内插A/D转换器。在预放大器阵列输出端引入失调平均网络,优化了预放大器阵列的输入对管尺寸,以补偿边界预放大器的增益衰减。在折叠电路中引入幅度补偿电路,以增加较小的电路功耗为代价改善了电路的带宽限制,提高了增益及输出线性范围。分析了内插平均电阻网路中的高倍内插误差,通过优化内插电阻值,实现了内插输出失调的减小,保证了系统良好的精度特性。仿真结果表明,在采样率为1GS/s、输入正弦波频率为465.82 MHz的条件下,该8位折叠内插A/D转换器的有效位数能够达到7.31位,功耗为290mW。Based on TSMC 0.18 μm CMOS process, an 8 bit 1 GS/s A/D converter with two-stage cascade folding and interpolating structure was proposed. An offset averaging network was used at the output of pre- amplifier array, and the size of input pair transistor of pre-amplifier array was optimized, so as to compensate the gain attenuation of boundary pre-amplifier. An amplitude compensation circuit was introduced in the folding circuit to lower the bandwidth limitation and increase the gain and output linear range with a small added power consumption. The errors of high interpolation coefficient in the interpolating average resistance network were analyzed. The size of interpolating resistance was optimized to decrease the interpolating output offset, so as to achieve better precision characteristics. Simulation results showed that the proposed 8 bit A/D converter could achieve an ENOB of 7.33 bit at an input signal sine wave frequency of 465.82 MHz and a sampling rate of 1 GS/s. The power consumption of the A/D converter was 290 mW.

关 键 词：折叠插值A/D转换器 级联结构 粗量化 细量化 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792